Testing of multi-chip modules (MCM) is made difficult by a number of factors; the density of chips on the modules leaves little space for any test circuitry, the close spacing of leads or pads on chips and the corresponding interconnects on the substrate complicates routing between test points of the MCM and the test circuitry, and the method of mounting and electrically connecting chips on an MCM can make some desired test points virtually inaccessible.
One attempt at solving these problems included placing the testing circuitry on the chip to be tested. Although this can provide access to test points internal to the chip, it also adds overhead to the chip, increasing its size and cost. Furthermore, the testing circuitry adds complexity to the chip which may not be removed when the chip is put into full production.
What is needed is technique for testing high-density multi-chip modules that can access test points hidden under chips and within areas of tightly spaced leads without adding cost or complexity to the modules when they are put into production.